1. Field of the Invention
This invention relates to FCCSP (Flip-Chip Chip-Scale Package) technology, and more particularly, to a flip-chip bonding structure on substrate for flip-chip package application, on which solder bumps can be bonded for electrically coupling a flip chip to the substrate.
2. Description of Related Art
FCCSP (Flip-Chip Chip Scale Package) is an advanced type of integrated circuit packaging technology that allows the overall package size to be made very compact. By FCCSP, the semiconductor chip is mounted in an upside-down manner over a substrate formed with an array of solder-bump pads, and which is mechanically bonded and electrically coupled to the substrate by means of solder bumps. A conventional flip-chip package configuration is schematically depicted in the following with reference to FIGS. 1A-1B.
FIG. 1A shows a schematic sectional view of a conventional flip-chip package configuration. As shown, the flip-chip package configuration includes a substrate 10 which is provided with an array of solder-bump pads 20 on the front surface thereof. As shown in the top view of FIG. 1B, these solder-bump pads 20 are arranged on the periphery of the substrate 10. By the FCCSP technology, a semiconductor chip 30 is mounted in an upside-down manner over the substrate 10 (i.e., with its circuit surface facing down against the front surface of the substrate 10), and which is mechanically bonded and electrically coupled to the substrate 10 by means of solder bumps 40.
Conventionally, there are many various ways of making the solder-bump pads 20, including, for example, the SMD (Solder Mask Define) method shown in FIG. 2A and the NSMD (Non-SMD) method shown in FIG. 2B.
Referring to FIG. 2A, the SMD method includes the use of a solder mask 51 having a circularly-shaped opening 52 to define solder-bump pad location. Further, a circularly-shaped electrically-conductive layer 53 is formed within the circularly-shaped mask opening 52 to serve as the intended solder-bump pad, and which is connected to an electrically-conductive trace 54.
The SMD method has the benefit of easy fabrication. However, one drawback to the SMD method is that it has poor routability to the electrically-conductive trace 54. One solution to the poor-routability problem is to use the NSMD method.
Referring to FIG. 2B, the NSMD method includes the use of a solder mask 61 having a circularly-shaped opening 62 to define solder-bump pad location. Further, a circularly-shaped electrically-conductive layer 63 is formed within the circularly-shaped mask opening 62, and an elongated electrically-conductive trace 64 is connected to the circularly-shaped electrically-conductive layer 63. The electrically-conductive trace 64 has an uncovered part 64a exposed through the mask opening 62 and a covered part 64b extending into the underneath of the solder mask 61.
It should be noted that, in the case of FIG. 2B, the combined surface area of the electrically-conductive layer 63 and the exposed portion 64a of the electrically-conductive trace 64 collectively serves as the intended solder-bump pad. In other words, the wetted solder would be spread over all exposed electrically-conductive surfaces, including the electrically-conductive trace 64 and the exposed portion 64a of the electrically-conductive trace 64.
The NSMD method has the benefit of allowing good routability to the electrically-conductive traces interconnecting the solder-bump pads on the substrate. One drawback to the NSMD method, however, is that the overall pad surface area would be affected by a positional deviation of the solder mask due to misalignment. This problem is described in more details in the following.
Theoretically, when a fixed amount of solder is wetted on a solder-bump pad, the degree of solder collapse would be substantially proportional to the overall surface area of the solder-bump pad. For this sake, in an array of solder-bump pads, if some pads are different in surface area from the others, the resulted array of solder bumps on these solder-bump pads would be non-coplanarized, which would lead to the problem of package warpage.
In addition, since the array of solder bumps are typically highly densified, any misalignment that causes the solder-bump pads to be increased in surface area would cause the attached solder bumps to be more horizontally extended, which would result in a short-circuit problem and a flip-chip underfill problem as illustratively depicted in the following with reference to FIG. 3.
FIG. 3 is a schematic diagram showing two neighboring solder-bump pads 71, 72 on which two respective solder bumps 81, 82 are formed. In the example of FIG. 3, the two neighboring solder-bump pads 71, 72 are circularly-shaped, which are fabricated through the NSMD method.
In FIG. 3, assume P represents the pitch between the two neighboring solder-bump pads 71, 72; D represents the diameter of each of the circularly-shaped solder-bump pads 71, 72: W represents the diameter of each of the solder bumps 81, 82; and G represents the width of the gap between the two solder bumps 81, 82. In a typical FCCSP layout, P=125 xcexcm, D=75 xcexcm, and W=93 xcexcm; and therefore, G=32 xcexcm. After reflow, however, the solder bumps 81, 82 will be further spread out horizontally, thus increasing W to about 105 xcexcm; and as a result, G is reduced to only about 20 xcexcm.
The narrowing of the gap G between the neighboring solder bumps 81, 82 would undesirably result in two problems. First, it would make the neighboring solder bumps 81, 82 more likely to be short-circuited to each other; and second, the narrowed gap G between the neighboring solder bumps 81, 82 would make subsequent flip-chip underfill process very difficult to implement.
It can be seen from FIG. 4A that, for the SMD-type of solder-bump pad shown in FIG. 2A (which includes only the circularly-shaped electrically-conductive layer 53), a positional deviation in the solder mask 51 would not affect the overall pad surface area.
However, for the NSMD-type of solder-bump pad shown in FIG. 2B (which includes the circularly-shaped electrically-conductive layer 63 and the exposed portion 64a of the electrically-conductive trace 64), it can be seen from FIG. 4B that a downward positional deviation in the solder mask 61 would cause part of the should-be-covered portion 64b of the electrically-conductive trace 64 to be exposed, thus giving an additional surface area to the solder-bump pad.
As mentioned earlier, a larger solder-bump pad would undesirably cause the attached solder bump to be more collapsed to a lower height, thus resulting a non-coplanarity problem to the resulted array of solder bumps.
Related patents are partly listed in the following:
U.S. Pat. No. 5,834,849 entitled xe2x80x9cHIGH DENSITY INTEGRATED CIRCUIT PAD STRUCTURESxe2x80x9d.
U.S. Pat. No. 5,637,832 entitled xe2x80x9cSOLDER BALL ARRAY AND METHOD OF PREPARATIONxe2x80x9d;
U.S. Pat. No. 5,783,865 entitled xe2x80x9cWIRING SUBSTRATE AND SEMICONDUCTOR DEVICExe2x80x9d;
U.S. Pat. No. 5,915,977 entitled xe2x80x9cSYSTEM AND INTERCONNECT FOR MAKING TEMPORARY ELECTRICAL CONNECTIONS WITH BUMPED SEMICONDUCTOR COMPONENTSxe2x80x9d;
U.S. Pat. No. 5,535,101 entitled xe2x80x9cLEADLESS INTEGRATED CIRCUIT PACKAGExe2x80x9d;
U.S. Pat. No. 5,011,066 entitled xe2x80x9cENHANCED COLLAPSE SOLDER INTERCONNECTIONxe2x80x9d.
U.S. Pat. No. 5,926,694 entitled xe2x80x9cSEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOFxe2x80x9d; and
U.S. Pat. No. 5,489,750 entitled xe2x80x9cMETHOD OF MOUNTING AN ELECTRONIC PART WITH BUMPS ON A CIRCUIT BOARDxe2x80x9d.
None of the above-listed patents, however, teach how to retain a solder-bump pad at its predefined surface area when the solder mask is deviated in position due to misalignment.
It is therefore an objective of this invention to provide a flip-chip bonding structure on substrate for flip-chip package application, which allows each solder-bump pad to retain predefined surface area even when solder mask is deviated in position due to misalignment.
It is another objective of this invention to provide a flip-chip bonding structure on substrate for flip-chip package application, which can help allow each attached solder bump to be reduced in horizontal extent as compared to the prior art, so that the attached solder bumps would be less likely short-circuited to each other.
It is still another objective of this invention to provide a flip-chip bonding structure on substrate for flip-chip package application, which can help allow each attached solder bump to be reduced in horizontal extent as compared to the prior art, so that the gap between neighboring solder bumps can be increased as compared to the prior art to facilitate flip-chip underfill.
In accordance with the foregoing and other objectives, the invention proposes a new flip-chip bonding structure on substrate for flip-chip package application.
Broadly defined, the flip-chip bonding structure of the invention comprises: (a) a solder mask having an opening shaped with an opposite pair of parallel straight edges including a first straight edge and a second straight edge; the location of the solder mask opening being subjected to deviation within a statistically-determined maximum positional deviation; and (b) an electrically-conductive layer which is predefined to have an exposed portion uncovered by the solder mask to serve as solder-bump pad and a pair of oppositely-adjoined unexposed portions including a first unexposed portion and a second unexposed portion covered by the solder mask to serve as electrically-conductive traces.
It is a key point of the invention that the solder-bump pad includes a first exposed parallelogram area adjoining the first straight edge of the solder mask opening, with an extent within the maximum positional deviation of the solder mask; a second exposed parallelogram area adjoining the second straight edge of the solder mask opening, with an extent within the maximum positional deviation of the solder mask; and an intermediate area between the first exposed parallelogram area and the second exposed parallelogram area; and the electrically-conductive traces include a first unexposed parallelogram area contiguous to the first exposed parallelogram area and adjoining the first straight edge of the solder mask opening, with an extent within the maximum positional deviation of the solder mask; and a second unexposed parallelogram area contiguous to the second exposed parallelogram area and adjoining the second straight edge of the solder mask opening, with an extent within the maximum positional deviation of the solder mask.
The foregoing flip-chip bonding structure of the invention can help retain predefined pad surface area even when the solder mask is deviated in position due to misalignment. Moreover, the flip-chip bonding structure of the invention can help allow each attached solder bump to be reduced in horizontal extent as compared to the prior art, so that neighboring solder bumps would be less likely short-circuited to each other and flip-chip underfill can be more easily implemented.